1. Field of the Invention
The present invention relates to a multilayered wiring structure in a semiconductor device and, more particularly, to a method of forming a multilayered wiring structure including a via hole. The present invention also relates to a semiconductor device having a characteristic multilayered wiring structure formed by this method.
2. Related Background Art
In recent years, a multilayered wiring technology has received a great deal of attention as a highly integrated high-density semiconductor element. In the multilayered wiring structure, different metal wiring layers are connected by using a via structure. The via structure in the multilayered wiring structure used in a conventional LSI having a design rule of 1 .mu.m or more is formed in the following process. A lower wiring layer is formed on the upper surface of a substrate, and a via hole is formed in an insulating interlayer formed on the lower wiring layer. Thereafter, a metal film is deposited in the via hole and on the insulating interlayer at the same time, and patterned to form an upper wiring layer.
In a micropatterned LSI, however, the yield and reliability of connection are greatly degraded in the via structure formed by this method. This is because the metal film to be formed into the upper wiring layer is normally deposited by using the sputtering method which is poor in step coverage, so that the metal film on the wall surface of the via hole becomes thinner to cause disconnection at this portion.
To solve this problem, for example, a method of forming a via hole into a tapered shape, or a method of improving step coverage by controlling the temperature of the substrate surface during deposition of an aluminum (hereinafter referred to as Al) alloy film to be formed into an upper wiring layer is proposed by S. R. Wilson et al., Proceeding of the Seventh International IEEE Multilevel Interconnection Conference, p. 42, 1990.
As a method of forming a via plug inside a via hole, a method of depositing a metal film serving as a barrier metal such as TiW inside the via hole and on an insulating interlayer, depositing a W (tungsten) film on the entire surface, and then, removing the W film from the insulating film is proposed by C. A. Bollinger et al., Proceeding of the Seventh International IEEE Multilevel Interconnection Conference, p. 21, 1990.
An interface between heterogeneous metals in the above-described via structure causes a deterioration in electrical characteristics in the via structure. For example, it is reported by S. R. Wilson et al., Proceeding of the Seventh International IEEE Multilevel Interconnection Conference, p. 42, 1990 that the via contact resistance in a via structure having a heterogeneous metal interface becomes higher than that in a via structure formed by contact of Al alloys.
In addition, it is reported by T. Kwok et al., Proceeding of the Seventh International IEEE Multilevel Interconnection Conference, p. 106, 1990 that, since the heterogeneous metal interface in the via structure causes discontinuity of the carrier movement in the wiring layer when a current flows, reliability against electromigration is greatly degraded as compared to a wiring layer on a flat substrate.
In Japanese Patent Laid-Open No. 63-260051, a method of forming a via plug consisting of Al which is selectively formable on the inner surface (side wall) of a via hole formed in an insulating interlayer on an Si substrate to form a via plug not only on the bottom portion but also on the side wall and bury the via hole.
A method of forming this via structure is shown in FIGS. 1 to 5.
As shown in FIG. 1, a lower wiring layer 300 and an insulating interlayer 40 are formed on an underlying insulating layer 20 formed on the surface of a substrate 10, and a via hole 50 is formed in the insulating interlayer 40.
As shown in FIG. 2, W silicide is then deposited to form a W silicide film 53a having a thickness of 50 nm on the entire surface of the insulating interlayer 40 by the CVD method.
As shown in FIG. 3, the W silicide film 53a on the upper surface of the insulating interlayer 40 and the bottom portion of the via hole 50 is etched by the reactive ion etching method (to be referred to as RIE hereinafter) to form the W silicide film 53a left only on the side wall of the via hole 50, thereby obtaining a via film 53b.
As shown in FIG. 4, Al is deposited and buried only in the via hole 50 by the selective CVD method to form a via plug 52. At this time, Al is deposited not only on the surface of the lower wiring layer 300 consisting of an Al alloy on the bottom surface of the via hole 50 but also on the surface of the via film 53a formed on the side wall of the via hole 50.
Finally, as shown in FIG. 5, the Al alloy is deposited by the sputtering method to form an Al alloy film having a thickness of 400 to 1,000 nm. The Al alloy film is formed into a predetermined pattern to form an upper wiring layer 60, thereby completing a semiconductor device having the via structure.
However, W silicide easily reacts with Al by annealing performed after formation of the via structure, so that a reacted layer is formed on the side wall of the via hole 50. Since the resistivity of the reacted layer is much higher than that of Al, the resistance of the via plug 52 is increased. In addition, the reaction between W silicide and Al may cause a change in volume to add a mechanical stress or form a cavity inside the via hole 50. These phenomena degrade the electrical characteristics of the via structure.